1. Field of the Invention
The present invention generally relates to a method of manufacturing semiconductor devices, and more particularly to a method of forming solder bumps with reduced undercutting of under bump metallurgy.
2. Description of the Related Arts
As integrated circuits(ICs) progress in the direction of high mounting density and large scale integration, semiconductor chips comprising a plurality of the ICs are progressing toward miniaturization, requiring an ever-finer pitch between bonding pads. The bonding pads serve as to location at which the circuitry of the semi conductor chip is electrically interconnected to external electronics via bonding wires. As the pitch between pads decreases with miniaturization, it becomes increasingly difficult to apply conventional bonding wires. The fine pad pitch causes several problems such as wire sagging, wire short, and so forth. Further, under the pressing demands of semiconductor products having high speed and high performance, the number of input/output (I/O) pads increases and lower inductance is required. Therefore, as a replacement of the conventional wire bonding technique, a flip chip technique or a DCA (Direct Chip Attachment) technique has been recently introduced.
In the well-known flip-chip technique, the chip is directly mounted to the substrate via solder bumps formed on its chip pads. The solder bumps are commonly formed using an evaporation or electroplating process. Fabrication of the solder bumps using evaporation is a simple process, but is not applicable to a chip having a fine pad pitch. For this reason, the electroplating process has become popular in the formation of the solder bumps.
Under bump metallurgy, referred to in the art as xe2x80x9cUBMxe2x80x9d, is formed between the solder bump and the chip pad. The under bump metallurgy is multi-layered and serves as an adhesion layer, a diffusion barrier, and a solder-wettable layer. A number of techniques are well known in the IC industry for formation of the under bump metallurgy and the solder bump. Typically, the under bump metallurgy is deposited as a continuous layer on the entire active surface of the wafer, and the solder bump is formed on the under bump metallurgy in a region over the chip pad. Following this, the under bump metallurgy is etched using the solder bump as an etch mask.
To carry out the etching of the under bump metallurgy, a dry etching or a wet etching method is used. Dry etching has certain drawbacks in that the bump can be damaged, and, due to anisotropic etching property, it is difficult to thoroughly etch the under bump metallurgy under the mushroom-shaped bump. For these reasons, wet etching has become the more popular technique. However, since wet etching has an isotropic etching property, the under bump metallurgy under the solder bump is often times undercut. As described above, the under bump metallurgy is multi-layered. Therefore, the undercutting of an upper layer of the under bump metallurgy influences a lower layer and thereby, the lower layer of the under bump metallurgy is more severely undercut.
FIGS. 1A and 1B are cross-sectional views illustrating a conventional method of forming solder bumps, and demonstrating resultant undercutting of the under bump metallurgy. With reference to FIG. 1A, a chip pad 12 is formed on an active surface of a semiconductor chip 10, followed by a passivation layer 14 and a buffer layer 16. The passivation layer 14 and the buffer layer 16 have openings for exposing the chip pads 12, respectively. The under bump metallurgy 18 is formed on the chip pad 12, the passivation layer 14 and the buffer layer 16, and comprises multiple layers 18a and 18b. A solder bump 20 is formed on the under bump metallurgy 16 over the chip pad 12.
The under bump metallurgy 18 is etched by using the solder bump 20 as a mask. As a result, as shown in FIG. 1B, each layer 18a, 18b of the under bump metallurgy 18 is undercut. The undercutting of the under bump metallurgy 18 decreases the joint area between the solder bump 20 and the under bump metallurgy 18, and the joint area between the under bump metallurgy 18 and the buffer layer 16. The reduction of the joint area between the under bump metallurgy 18 and the solder bump 20 in turn decreases the height of the solder bump 20. The resultant height of the solder bump 20 formed during a reflowing process depends on the degree of the undercutting of etched under bump metallurgy. Further, the reduction of the joint area between the under bump metallurgy 18 and the buffer layer 16 diminishes the shear strength of the bump 20. The above-described undercutting of the under bump metallurgy 18 mechanically and electrically degrades the reliability of the bump. That is a common defect of the flip chip technique, so-called, controlled collapse chip connection-C4 technique.
A technique for mitigating the above-described shortcomings is disclosed in European Pat. No. 0603296 issued to MCNC Research Triangle Park. In accordance with this technique, prior to etching the under bump metallurgy, the solder bumps are melted to form an intermetallic compound layer on an interface between the solder bump and the under bump metallurgy. Following this, the under bump metallurgy is etched by using the intermetallic compound layer as a mask. In order to prevent flow of the molten solder of the bumps into the under bump metallurgy, solder dams are formed on the under bump metallurgy at regions between the bumps. This technique has certain drawbacks in that it further requires additional steps of forming and removing the solder dams, and this dam structure cannot be applied to formation of a chip having a fine bump pitch.
U.S. Pat. No. 5,902,686 issued to MCNC Research Triangle Park, also discloses etching of the under bump metallurgy using an intermetallic compound layer as a mask. Herein, the intermetallic compound layer is made by melting the solder bump prior to etching the under bump metallurgy. According to this technique, an oxidation layer is formed in replacement of the solder dams for preventing of flow of the molten solder. Since the oxidation layer is formed on the upper surface of the under bump metallurgy, in particular, the copper layer, as well as on the solder bump, this technique also requires an additional step of removing the oxidation layer prior to etching the under bump metallurgy.
Accordingly, an object of the present invention is to provide a method of forming solder bumps, which can increase joint area between the solder bump and the under bump metallurgy, and thereby reduce the undercutting of the under bump metallurgy.
Another object of the present invention is to reduce the undercutting of the under bump metallurgy by forming an intermetallic compound layer having a greater size than the diameter of the solder bump on an interface between the solder bump and the under bump metallurgy and etching the under bump metallurgy using the intermetallic compound layer as a mask.
Still another object of the present invention is to simplify the process of forming the solder bumps without the need for the additional steps of forming and removing the solder dams or the oxide layer as required by the conventional technique described above.
The foregoing and other objects are achieved by a method of forming solder bumps formed on an active upper surface of a semiconductor device including a plurality of chip pads. An under bump metallurgy (UBM) is formed on a surface of the semiconductor device including the chip pads. Photoresist patterns are formed on the under bump metallurgy, the photoresist patterns exposing the under bump metallurgy. Solder bumps are formed on the under bump metallurgy exposed by the photoresist patterns. The photoresist patterns are removed, and an intermetallic compound layer is formed on an interface between each solder bumps and the under bump metallurgy by heating the solder bumps at a temperature lower than a melting point of the solder bumps. The under bump metallurgy is etched using the intermetallic compound layer as a mask, and the solder bumps are reflowed.
An insulation layer may be formed on the upper surface of the semiconductor device, the insulation layer having openings for exposing the chip pad. The under bump metallurgy may be formed on the insulation layer and the chip pad. The insulation layer may comprise a passivation layer and a buffer layer, the passivation layer comprising an oxide layer or a nitride layer and the buffer layer comprising a polymer selected from the group consisting of polyimide, benzocyclobutene(BCB), polybenzoxazole(PBO), and epoxy.
The under bump metallurgy may comprise a first metal layer on the upper surface of the semiconductor device including the chip pads, and a second metal layer formed on the first metal layer. The first and second metal layers may be respectively comprised of a metal selected from the group consisting of chromium(Cr), copper(Cu), nickel(Ni), titanium(Ti), tungsten(W), vanadium(V), palladium(Pd), aluminum(Al), gold(Au), and their alloys.
The under bump metallurgy may be formed of a nickel layer on the upper surface of the semiconductor device including the chip pads, and a copper layer on the nickel layer. The intermetallic compound layer may be formed of a copper-tin(Cuxe2x80x94Sn) intermetallic compound layer on the interface between the solder bumps and the copper layer.
The solder bumps may be formed by plating solder on the under bump metallurgy exposed from the photoresist patterns. The solder bumps may have a melting point of approximately 320xc2x0 C., in which case, the intermetallic compound layer is formed by heating the solder bumps at approximately 300xc2x0 C. In the case where the solder bumps have a melting point of approximately 183xc2x0 C., the intermetallic compound layer may be formed by heating the solder bump to approximately 170xc2x0 C. The intermetallic compound layer preferably extends beyond the diameter of the solder bumps prior to reflow of the solder bumps.
In an alternative embodiment, the present invention comprises a method of forming solder bumps on an active upper surface of a semiconductor device including a plurality of chip pads. An insulating layer is formed on an active upper surface of a semiconductor device including the chip pads. An under bump metallurgy (UBM) is formed on the insulating layer, the under bump metallurgy having a relatively deep profile between an upper portion above the insulating layer and a lower portion on the chip pads. Photoresist patterns are formed on the under bump metallurgy, the photoresist patterns exposing the under bump metallurgy. The solder bumps are formed on the under bump metallurgy exposed from the photoresist patterns. The photoresist patterns are removed, and the solder bumps are heated to a temperature higher than a melting point of the solder bumps, the heating forming an oxide layer on the under bump metallurgy. The oxide layer and the under bump metallurgy are etched using the solder bump as a mask; and the solder bumps are reflowed.
In a preferred embodiment, the insulation layer is of a thickness much larger than the thickness of the under bump metallurgy.